1. Field of the Invention
The present invention is directed to a microcontroller in which the low order address bits are directly driven and, more particularly, to a microcontroller in which the fetch cycle is shortened when the fetch address is sequential with the prior fetch address.
2. Description of the Related Art
Microcontrollers typically operate in a mode where instructions and data are fetched from an external memory in a sequential order for a large proportion of any period of execution. These microcontrollers typically time division multiplex address and data bits over some or all of the same external lines or pins to conserve external pin use. Because the same pins are used for both address and data, an external address latch is provided between the microcontroller and the external memory. This external latch stores the address output by the microcontroller and presents it to the memory while the external pins are used for data, so that the address can be applied to the memory throughout the read cycle. Each of the fetch cycles occupies several clock cycles one of which is a clock cycle where a latch enable signal is provided to the external latch. Because microcontrollers are being requested that operate at higher and higher speeds there is a need to reduce the number of clock cycles required for an instruction or data fetch and a need to speed up or optimize the fetch cycle.
Some microcontrollers directly drive address bits at the high order portion or most significant bits (MSB) of the address. However, because the high order address bits change relatively infrequently during sequential address fetches reducing address latching for the high order bits is not particularly helpful in reducing the length of a fetch cycle.
What is needed is a method of directly driving the low order or least significant bits (LSB) of the address in a way that reduces the cycle time for a fetch.